The present invention relates generally to semiconductor structures and methods for fabricating those structures. Particularly, the invention relates to a semiconductor structure and a method for laterally oxidizing nFET high-k gate stacks.
As integrated circuits become smaller, maintaining semiconductor device performance and controlling threshold voltage becomes more difficult. Field Effect Transistors (FET), which lie at the core of an integrated circuit, typically are characterized by being of a hole conduction type, called pFET, or being of an electron conduction type, called nFET. It is known in the art that decreasing the size of a FET device leads to a decrease in controlling their performance. This is due in part to the thickness of the gate dielectric component becoming thinner as the size of the FET device decreases. Once the gate dielectric becomes too thin leakage begins to reach unacceptable levels and large currents may be able to flow through the dielectric material via direct tunneling. As a result, improving semiconductor device performance without decreasing the thickness of the gate dielectric has become increasingly important.
As is known to those skilled in the art of semiconductor design and fabrication, one such method for improving performance of a FET while maintaining adequate gate dielectric thickness is by replacing the traditional gate dielectric material with another material having an acceptable equivalent oxide thickness (EOT). An acceptable EOT is achieved by using a material that has a greater dielectric capacitance than the traditional gate dielectric material, thereby permitting the substitute material to have a greater thickness while maintaining a reaction speed comparable to that of the traditional gate dielectric material. Suitable materials are characterized as having a high dielectric constant, “k”. Accordingly such materials are known in the art as “high-k” materials. A high-k value is one that is greater than the dielectric constant of the traditional gate dielectric material silicon dioxide, which is approximately 3.9. While high-k materials must provide an increased dielectric capacitance, utilizing such materials is known in the art to often result in a threshold voltage (VT) that is different from what is desirable from a circuit perspective. As a result, a method for controlling VT of high-k gate dielectric FET devices has become increasingly sought after.
Controlling VT in high-k dielectric FET devices is particularly significant for complementary metal oxide semiconductor (CMOS) devices because CMOS devices operate at lower voltages, and as the operating voltage of a semiconductor device decreases, VT also must decrease, and consequently, variations in VT become less tolerable. VT is affected by known factors, but as the size of FET devices has decreased, the traditional methods of setting VT (i.e., adjusting body and channel doping) have become less effective. One method for controlling VT with high-k gate dielectric FET devices utilizes an additional material layer known in the art as a “capping layer”. However capping layers can have undesirable effects, such as increasing EOT or degrading carrier mobility. Furthermore, different capping layers are often desired for n-type FET (nFET) and p-type FET devices (pFET) devices, requiring complex and costly integration schemes.
Another known method for controlling VT that remains promising is oxidation of the gate dielectric. Oxidation of the high-k dielectric layer directly affects VT and has proven to be very effective for intentionally tuning VT of FET devices. However, while oxidation of high-k gate stacks is known to benefit the VT of p-type FET devices (pFET), it also is commonly thought to degrade the VT of nFET devices. Unintentionally filling oxygen vacancies in nFET gate stacks during device processing can make the VT of the resulting nFET devices dependent on device-width. Therefore, not only must fabrication of CMOS devices be tailored to prevent oxidation processes that benefit pFET devices from also oxidizing nFET gate stacks, but fabrication processes must also be selected to prevent nFET gate stacks from being unintentionally exposed to processes and environments that may result in device-width dependence.
The prior art includes methods for fabricating semiconductor circuits containing both nFETs and pFETs (e.g., CMOS circuits) that involve exposing high-k dielectric layers of gate stacks to oxygen if those gate stacks are intended to be fabricated into pFETs, while simultaneously keeping high-k dielectric layers of other gate stacks unexposed to oxygen if the other gate stacks are intended to be fabricated into nFETs. These methods frequently require the implementation of additional processing steps and materials for the sole purpose of regulating which gate stacks are, and are not, exposed to oxidation processes as well as unfavorable environments, which in turn increases the complexity and expense of fabricating semiconductor devices containing both nFETs and pFETs.